RISC V Instruction Set Architecture Explained
The RISC V (pronounced risk-five) Instruction Set Architecture is rapidly gaining popularity in the field of Computer Science & Engineering. Tech giants like Google, NVIDIA, Qualcomm & IBM are members of the RISC V Foundation, the organization behind the RISC V ISA. Today, we will take a look at what RISC V is, why we should support it and how it is better than the other ISAs currently in use.
What is an Instruction Set Architecture?
In simple terms, An Instruction Set Architecture is a set of commands (opcodes) and machine codes that is supported by a processor. It is the boundary between software & hardware from a programmer’s point of view.
In even simpler terms, it is an agreement on how software will communicate with the processor.
The Instruction Set Architecture is abstract as it only defines the Instructions that need to be available which implies that the implementation of the instructions might vary. An example of this would be the ADD mnemonic. The ISA only specifies that an ADD instruction should be available. It does not define the circuitry or Implementation of the ADD instruction. So the ADD instruction maybe implemented using the Look Ahead Adder or the Ripple Carry Adder.
This means that differently manufactured hardware using the same instruction set architecture will be capable of running any compiler or software written for that particular ISA.
Types of Instruction Set Architectures
The most popular types of ISAs include
- CISC – Complex Instruction Set Computing
- RISC – Reduced Instruction Set Computing
- EPIC – Explicitly Parallel Instruction Computing
Out of the three, we will be discussing about CISC & RISC as their significance is higher in today’s topic of dicussion, the RISC V.
CISC – Complex Instruction Set Computing
Complex Instruction Set Computing is a type of ISA where a single instruction is capable of performing multiple low level operations. A CISC machine instruction is converted to microinstructions before execution.
Since a CISC instruction has to perform multiple low level operations, it takes up multiple clock cycles for completion of execution.
Optimization of CISC Architecture can only be done through hardware refinement. CISC processors these days have over a thousand instructions which were added over the years to meet the requirements without removing the already existing ones to provide for backwards compatibility. As the instructions keep increasing in number, the processor keeps getting slower. To maintain the same level of performance, the hardware needs to be innovated and optimized. This means, as hardware gets better, the ISA keeps getting worse which isn’t sustainable growth.
RISC – Reduced Instruction Set Computing
Reduced Instruction Set Computing is a type of ISA wherein the instructions perform only very simple tasks and the number of instructions are very less.
Since the instruction operations are simple, the execution time is significantly lesser than the instructions of a CISC ISA Implementation.
Moreover, the RISC Instructions need not be compiled to microinstructions before execution and instead can be executed directly. More complex operations are achieved in a RISC ISA by pipelining multiple instructions together. Since the instructions themselves are very simple and take less time to execute, even the pipelined instructions are capable of being executed in almost a single clock cycle.
Why RISC V?
Intel uses the x86 ISA for all of its processors which is a CISC ISA and has gotten very complex over time. The complexities have led to various performance and security issues. The Spectre Vulnerability for instance, discovered in early 2018 has affected millions of devices that have a branch predictor built into the processor, world wide.
RISC V seems to offer a sustainable solution to the problems we face today as consumers, engineers and developers. The two main reasons why RISC V has received support from all around the world are:
- RISC V is completely Open Source.
- RISC V is more efficient than today’s sluggish CISC based processors.
What does it mean for an ISA to be open source?
An open source ISA is a specification that is available freely for adoption, extension and implementation by any microprocessor manufacturer. When the ISA is available openly, the chances of a bug remaining undiscovered is highly unlikely which is a huge win for both the consumer and the manufacturer.
Why is RISC V more efficient than CISC ISAs?
All of the advantages that RISC has over CISC can be used as an argument to this question.
- RISC does not require separate memory to execute
- RISC Instructions can be executed directly unlike CISC instructions which need to be converted to microinstructions before execution.
- Addition of complexities in RISC can be done through software modification unlike CISC where extension of functionality requires hardware level changes.
All of the above solutions offered by RISC V points towards RISC V being the next big thing in the field of Classical Computer Engineering. I am an untiring advocate of the Open Source World which RISC V has become an important member of.
what do you think of RISC V? Will it be the next big thing? Leave your suggestions in the comments below.